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consider a system with a two-level cache having the following characteristics: l1 cache has an access time of 1 clock cycle with an average hit rate of 95%; l2 cache has an access time of 5 clock cycles (after l1 miss) with an average miss rate of 10%. if l2 misses take 40 clock cycles, what would be the average memory access time in clocks?
Sagot :
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