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For a processor with primary and secondary caches, an instruction cache miss rate of 1%, a data cache miss rate of 5%, a instruction mix of 40% data accesses, a primary to secondary cache miss penalty of 10 cycles and a secondary cache to main memory miss penalty of 200 cycles and a secondary miss rate of 0.2%, what will be the contribution to total CPI from the cache misses (in decimal)

Sagot :

Answer:

The answer is "0.306".

Explanation:

The Primary to Secondary Memory Instruction miss cycle

[tex]= I \times 0.01 \times 10 = 0.1 I[/tex]

Data miss cycles[tex]= I \times 0.05 \times 10 \times 0.40 = 0.2 I[/tex]  

The Secondary to main Memory Instruction miss cycle[tex]= I \times 0.01 \times 200 \times 0.0002 = 0.004 I[/tex]

Data miss cycles[tex]= I \times 0.05 \times 200 \times 0.0002 = 0.002 I[/tex]

Total memory stall cycle [tex]= ( 0.1 + 0.2 + 0.004 + 0.002 ) I =0.306 I[/tex]

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