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Design the following circuit in Verilog, be careful with syntax and all language rules, commas, semicolons etc. (Any mistake, even if small, will result in deductions) Use async/active-low reset for all flip-flops. (Note: thick wires represent 4 bit connections...) XIN[3:0] MUX data_in[3:0] XOUT[3:0] D Q CLK ARSIN CLK ARSTN SEL

Sagot :

Below is the design of the circuit in Verilog, with syntax and all rule of language like commas, semicolons etc.

VERILOG CODE IN STRUCTURAL MODEL:

1) VERILOG CODE OF D FLIP FLOP

module DFF (CLK, D, ARSTN, Q);

input CLK, D, ARSTN;

output Q;

reg data = 1'b0;

  if (ARSTN)

      data <= 1'b0;

  else

      data <= D;

assign Q = data;

endmodule

2) VERILOG CODE OF MUX

module MUX (d0, d1, SEL, Y);

input d0, d1, SEL;

output Y;

assign Y = SEL ? d0 : d1;

endmodule

3) VERILOG CODE OF TOP FILE

module circuit (XIN, data_in, CLK, ARSTN, SEL, XOUT);

input XIN, data_in, CLK, ARSTN, SEL;

output XOUT;

wire s0, s1;

DFF UUT0 (CLK, data_in, ARSTN, s0);

MUX UUT1 (XIN, s0, SEL, s1);

DFF UUT2 (CLK, s1, ARSTN, XOUT);

endmodule

OUTPUT:

To know more about VERILOG, visit: https://brainly.com/question/24228768

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